Practical Insights on High Speed Design
The EEs at Mindtribe have a tradition called the Elusive Steak Dinner, detailed in Adam’s blog post ESD-Compliant Design (it’s not what you think). In his post, Adam discusses the three golden rules that we at Mindtribe follow to increase odds of an error free design: Peer Review, Leverage Past Work, and Thorough Part Verification. I recently achieved my first ESD-Compliant Design due to following these rules and a lot of collaboration with my project team. While all three are important I found golden rule #2: Leverage Past Work, particularly useful for this design.
For me, part of leveraging past work is referring back to my ever growing running notes on various subjects. I even maintain a commonly used circuits catalog (but that’s another post). Since this board was an adventure in high speed design, let’s look at a few of the tidbits I found useful from my notes.
What is high speed?
This may seem trivial, but how do you know when you are creating a high speed PCB and why does it matter? There are a few ways to think about this. For a general rule of thumb some sources state that it’s time to consider your design high speed once a trace will be more than ⅓ the rise time (of the device switching speed) long.
To calculate this we need to look at propagation velocity.
Where Vp is propagation velocity, c is the speed of light, and εR is the dielectric constant
To find the length at which a design becomes high speed:
Where tr is the rise time of the signal
Other sources take a more general approach of talking about lumped versus distributed circuits. Systems physically small enough for all points to react together with a uniform potential are called lumped systems. The idea is that small structures are lumped circuits while big ones are distributed. You’ll also see this described in terms of propagation delay. Once you’re in distributed territory, you’re talking about high speed.
My favorite visualization of this concept is from “High-Speed Digital Design A Handbook of Black Magic” by Johnson and Graham
I’m designing a high speed PCB. So what?
The higher switching speeds are, the more radiation occurs on the PCB. This radiation can be extremely disruptive. A device can cause interference through a coupling path and can be affected by interference through the coupling path. The coupling in a path can be capacitive, inductive, conductive or radiative. When radio frequency energy interferes with the operation of an electronic device we call that electromagnetic interference or EMI. The ability of an electronic device to operate without causing EMI and without being affected by EMI from other devices is called electromagnetic compatibility or EMC. EMC is a lengthy topic on it’s own. In fact, on my desk there’s an entire book devoted to the subject, “Introduction to Electromagnetic Compatibility” by Clayton R. Paul and another by Henry W. Ott in our lab.
Start with a plan
This isn’t exactly in my notes, but I didn’t want to skip it. Always start with a plan. Think critically about your design before you get to your layout. Your plans may change and adapt as you learn more about your design, but don’t use that as a reason to not plan in the first place. Take notes on major design considerations so that you have them handy in the future. On my list of things to plan at this stage are:
- Signal speed – determine the high frequency and fastest rise time signals
- Sensitive signals – create preliminary plans to meet the requirements for signals that are differential, controlled impedance, terminated, trace length/propagation delay sensitive, clocks, buses, etc.
- Power supply – document required voltages and power specifications for all ICs, start planning your power planes – are split planes possible/necessary?
- System interconnections – develop diagrams that help visualize the critical interconnections where you’ll need to think about return currents and crosstalk
Choose your board stackup
Take ample time to choose an appropriate board stack-up and document your fabrication requirements. This is a great time to clarify fabrication capabilities with your PCB manufacturer and adjust all of your design rules to match. In my notes about stackup I reference Henry Ott’s five objectives:
- A signal layer should always be adjacent to a plane.
- Signal layers should be tightly coupled (close) to their adjacent planes.
- Power and Ground planes should be closely coupled together.
- High-speed signals should be routed on buried layers located between planes. In this way the planes can act as shields and contain the radiation from the high-speed traces.
- Multiple ground planes are very advantageous, since they will lower the ground (reference plane) impedance of the board and reduce the common-mode radiation.
In the case of this design I chose an 8-layer stack-up since that is the thinnest possible stack-up that would achieve all of the objectives and would accommodate my design needs. Use elements identified in your plan to help guide your stackup selection. Keep in mind that you’ll need at least one complete, uninterrupted, ground plane to serve as a reference for your sensitive traces identified in your plan.
Mind your ground planes
Avoid split ground planes if you can. This means don’t route signals on your ground plane and avoid multiple grounds if you can. If creating a slot in your ground plane is unavoidable, signal traces must not be routed over the slot. There are several reasons for this. Split ground planes can act as a slot antenna. Additionally, if a signal is routed over a slot, the signal’s return current path has to go around the area creating a larger loop area. The larger the loop area, the more EMI problems occur. This can be in the form of induced noise into the other part of the split plane or crosstalk in the return current path.
Your initial plan with system interconnections is critical for your ground planes. Keep functional blocks that are analog together and functional blocks that are digital together. Place functional functional blocks together and route the signals for the blocks only within their own region. Be careful with return current paths and crosstalk if you have interconnections between digital and analog functional blocks.
Additionally, there are many considerations when connecting to ground and power planes:
- Add all of the recommended decoupling capacitors and place them as close to the pins of the device as possible. Keep in mind that sometimes the closest possible location is on the other side of the board under the chip.
- Use low ESR capacitors
- Place vias adjacent to capacitor pads and use a bigger via size to minimize the inductance in decoupling capacitors
- Use wide, short traces between ground vias and ground pin pads – the same goes for power pins
- Connect each ground pin to the ground plane individually, do not daisy chain.
Mind your routing
Another critical area in the success of a high speed design is signal routing. I’m only going to scratch the surface on routing guidelines here. Heck, differential routing and RF or antenna traces probably each deserve their own section. But, here are a few points that will help you start down the right path:
- Keep your traces as far apart as possible – don’t pack them in if you don’t have to
- Minimize long, parallel or coupled sections between nets
- Route signals on different layers orthogonal to each other. I’ll often define alternating signal layers as being horizontally or vertically routed.
- Avoid 90 degree angle bends in your traces
- Avoid using vias for critical signals like clock transmission lines.
- Follow best practice differential routing rules like maintaining equal line lengths, maintaining spacing, and avoiding vias.
- Carefully design transmission lines. Try to keep the conductor as close to the ground plane as possible.
This post just grazes the surface on high speed design. If you’re delving into your first high speed PCB, leverage as many resources as possible. Not only are there several good books on the topic, but also a plethora of application notes from various IC manufacturers. As for me, while leveraging my running list of notes wasn’t the only reason I achieved an ESD-compliant design, I think I’ll continue to add to it as I learn from each new project.